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no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a W9980 digital voice record W9980 digital voice record er er general applications: W9980 was specially designed for long duration digital reco ding appliance using nvm as the storage device. the typical applications are included voice recorder, language learning tool, voice notebook, and high quality voice toy.
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a 1 general description the W9980d is dsp base digital voice recorder chip. this chip compress and decompress sampled voice data by the algorithm g.723.1 and get high quality voice data for play or for voice to text translate. the w9990d integrate interfaces for dvr application and minimize pc board area. this chip build in good power management and suitable for portable machine design. the voice sampling rate for itu - g.723.1 can be 8k or 11k and support 5.3k/6.3k bit rate for 8k sampling rate or 7.3/8.7k data rate for 11k sampling rate. the compression rate is 24 or 20 for the two bit rate. the itu - g.723 get high quality voice compress data and suitable for voice recognition after decompress. the W9980d build in uart and parallel port interface to pc host, the compressed data can upload to pc for voice mail or for voice to text translation by ibm via - voice softwar e. the W9980d integrate synchronous serial port to interface external codec for voice sample and play, lcd interface, pio interface for user interface and memory interface for voice data recorded. the memory controller can interface to smartmedia, compact flash, ide, or intel/amd type flash memory. in addition to receive bit stream from external codec, this chip can receive bit stream from the 8032/8051 mode 0 serial port by the synchronous serial port interface to these external micro controller. the W9980 d is a 3.3v device with ttl compatibility 3.3v only i/o, and is packaged in a 128l lqfp.
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a 2 features q dsp core 30 mips 24 - bits instruction, 16 - bits integer data dsp core internal one instruction and two data access at one cycle build - in two b ank instruction rom. 13kx24 and 4kx24 build - in 8kx16 rom and 4kx16 sram for 1st data access build - in 2kx16 rom and 1kx16 sram for 2nd data access external data memory extension with 2k base up to 16m words three interrupts support (irq0_, irq1_ and irq2_) low power consumption - 50ma during operation power down mode support - 30ua during power down q codec interface synchronous serial port connecting external codec device for voice input and sound play q memory interface support smartmedia and compactflash interface for voice recorded with no size limitation support amd/intel type flash memory interface for voi ce recorded up to 16mwords on 2k words base. q lcd interface support 1/3 bias (1, 2, 3 volt) 1/4 duty tn - lcd interface up to 100 lcd dots (4com * 25 segment) support serial interface to external lcd driver up to 160 dots q gpio interface 12 gpios for key - pad and system control
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a gpio input change from low - to - high and high - to - low generate different interrupts to dsp core (irq0_ and irq1_) q host interface ns16550 compatible uart support for pc data upload/download ieee 1284 parallel port byte mode support for pc data upload/download q up 8051/8032 serial mode interface support 8051/8032 synchronous serial bitstream for data decode q operation frequency is 30mhz q 3.3v device with ttl - compatible 3.3v i/o q 128l lqfp package q compression algorithm provide itu - g.723.1 (5.3k/6.3k bit rate) voice coding/decoding programmable voice sampling rate. 8k for normal mode recording and 11k for precise mode recording provide silence - detection and comfort - noise - generation to length en the recording time q user interface categorize messages : provide 4 folders to store different kinds of message and up to 99 records for each folder tape - recorder/cd type operation : provide keys 2 record 2 , 2 play 2 , 2 stop 2 , 2 pause 2 , 2 forward 2 , 2 backward 2 , 2 erase 2 , and 2 erase all 2 operation voice editing append : each record can be appended by new message voice editing delete : each record message can be deleted fast scan : play first 5 second of each record for message search date and time stamp : every record is ind exed by 2 data 2 , 2 time 2 and 2 time - spend 2 stamp reserved recording time : t he ui display the 2 reserved recording time 2 to indicate available time for recording
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a alarm clock : provide 4 time zones up to 80 sets of alarm clock (20 sets/zone) voice alar m : alarm by voice message or beeps up/download : voice message upload/download to pc low power detection : warning message if battery low. automatic power - down : system power - down if 5 minutes no operation
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a 3 pin configuration the W9980d is packaged in a 128l lqfp. the pin configuration is shown in figure 3.1 dvr 128-pin lqfp 1 5 10 15 20 25 30 3 5 4 0 5 0 5 5 6 0 65 75 80 85 95 1 0 0 1 0 5 1 1 0 1 1 5 1 2 0 vss vdd v d d r f s 0 d r 0 s c l k 0 s e g 1 vss dh1 vss 4 5 vdd seg18 seg19 ma3 ma4/up_data ma5/up_clk ma6/up_req ma7/nfaut ma8/pe ma9/sel ma10/busy ma11/nack seg21 seg20 v s s vdd vdd 1 2 5 70 90 ma12/nseli ma13/ninit ma14/naufd ma15/nstb ma16/pd0 ma17/pd1 ma18/pd2 ma19/pd3 ma20/pd4 ma21/pd5 ma22/pd6 ma23/pd7 md0 md1 vss m d 5 m d 9 m d 1 0 m d 1 1 m d 1 2 m d 1 3 m d 1 4 m d 1 5 v d d v s s v s # c e 0 # c f | r s t / w p # v s s v d d c d 1 # b u s y # c d 2 # p w r f # r e s e t # x t a l c l k i n x t a l 3 2 c l k 3 2 k p i o 1 1 p i o 1 0 p i o 9 p i o 8 p i o 7 v s s v d d m c l k t f s 0 d t 0 dh2 vlcd3 vlcd2 vlcd1 seg16 seg17 seg14 seg15 seg13 seg11 seg12 seg10 s e g 0 p i o 6 p i o 5 p i o 4 seg22 seg23 seg24 s i n / w c l k s o u t / w d a t a seg6 seg5 seg4 seg9 seg8 seg7 seg3 seg2 c o m 3 c o m 2 c o m 1 c o m 0 m d 8 m d 7 m d 6 m d 4 m d 3 ma2 ma1 ma0 we# p i o 3 p i o 2 p i o 1 p i o 0 w a i t # r e g # / a l e c e 2 # / c l e c e 1 # m d 2 oe# figure 3.1 W9980d pin configuration
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a 4 pin description the following signal types are used in these description. i input pin iu input pin with internal pull - up resistor b bi - direction input/output pin o output pin aio analog input/output pin p power supply pin g ground pin 4.1 pin definition lcd interface pin name pin number type description com0 - com3 59 - 62 o lcd panel common pins. (1/3 bias, 1/4 duty) seg0 - seg24 63 - 76, 78 - 79, 81 - 89 o lcd panel segment pins. (1/3 bias, 1/4 duty) vlcd3 91 p lcd voltage pin must connect to 3~3.3 v vlcd2 92 i for lcd voltage level shift during display (2v) vlcd1 93 i for lcd voltage level shift during display (1v) dh2,dh1 94,95 i connect a capacitor to both pins, used for the lcd double voltage capacitor. sin / wclk 56 i o this pin play the uart sin signal if external lcd driver function off is the external lcd driver clock pin if external lcd driver function on sout / wdata 57 o this pin play the uart sout signal if external lcd driver function off
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a it is the external lcd driver serial data pin if external lcd driver function on gpio interface pin name pin number type description pio0 97 b gpio pin used as mode key by ui pio1 98 b gpio pin used as erase key by ui pio2 99 b gpio pin used as set key by ui pio3 100 b gpio pin used as stop key by ui pio4 101 b gpio pin used as rec key by ui pio5 103 b gpio pin used as play key by ui pio6 104 b gpio pin used as rew key by ui pio7 106 b gpio pin used as ff key by ui pio[8:11] 107 - 110 b gpio pins codec interface pin name pin number type description mclk 49 o master clock output to external codec dr 50 i serial data received from codec rfs 51 b receiver frame sync of codec serial port sclk 52 b serial clock of codec serial port tfs 53 b transmitter frame sync of codec serial port dt 54 o serial data transmitted to codec
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a memory interface pin name pin number type description cd2# 118 iu card detected 2 from compactcard cd1# 118 b card det ected 1 from compact card. in test mode 0 this pin is external instruction rom cs_ and in test mode 1 used as internal instruction rom0 cs_ busy# 120 iu external flash rdy/busy_ signal. in test mode 1 this pin used as internal sram2 cs_ wait# 121 iu wa it state insert signal used to lengthen the external data memory bus cycle vs# 123 i 2 voltage sense 1 2 from compactflash card. this signal should be grounded by cfc to indicate initially 3.3v ope ration cf_rst / wp# 124 b compactflash card reset or smartmedia write - protect signal. this signal is direct drive by the register cf_rst or wp# on 0x3e03. in test mode 0 is used as external 2nd data memory cs_. in test mode 1 is used as internal 2nd data rom cs_ reg# / ale 125 o compactflash reg# signal, this signal direct inverse drive by register reg_en on 0x3e03 smartmedia flash ale , indicate address cycle ce2# / cle 126 o ce2# is one of external memory cs_ signal. it active if external memory access and register ce2_en on 0x3e03 is enable smartmedia flash cle, indicate command cycle. ce1# 127 o ce1# is one of external memory cs_ signal. it active if external memory access and register ce1_en on 0x3e03 is enable ce0# 128 b ce0# is one of external memory cs# signal. it active if external memory access and register ce0_en on 0x3e03 is enable in te st mode 0 is used as external 1st data memory cs_. in test mode 1 is used as internal 1st data ram cs# oe# 1 b external memory oe# signal
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a in test mode 1 is used to read internal memory we# 2 b external memory we# signal in test mode 1 is used to write internal memory ma0 - ma3 3,4,5,6 b external memory address 0 - 3 in test mode 1 is internal memory address 0 - 3 ma4 / up_data 8 b external memory address 4 if register upic_en on register 0x3e21 disable in test mo de 1 is internal memory address 4 this pin get external synchronous serial data if upic_en enable (8051/8032 serial mode 0) ma5 / up_clk 9 b external memory address 5 if register upic_en on register 0x3e21 disable in test mode 1 is internal memory addres s 5 this pin is external synchronous serial clock in if upic_en enable (8051/8032 serial mode 0) ma6 / up_req 11 external memory address 6 if register upic_en on register 0x3e21 disable in test mode 1 is internal memory address 6 this pin is external sy nchronous serial clock in if upic_en enable (8051/8032 serial mode 0)port data in if upic_en enable (8051/8032 serial mode 0) ma7 / nfaut 12 b external memory address 7 if register ppic_en on register 0x3e03 disable in test mode 1 is internal memory add ress 7 this pin drive the signal nfault on parallel port if ppic_en enable (parallel port interface enable) ma8 / pe 13 b external memory address 8 if register ppic_en on register 0x3e03 disable in test mode 1 is internal memory address 8
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a this pin driv e the signal perror on parallel port ma9 / sel 14 b external memory address 9 if register ppic_en on register 0x3e03 disable in test mode 1 is internal memory address 9 this pin drive the signal select on parallel port ma10 / busy 15 b external memory a ddress 10 if register ppic_en on register 0x3e03 disable in test mode 1 is internal memory address 10 this pin drive the signal busy on parallel port ma11 / nack 16 b external memory address 11 if register ppic_en on register 0x3e03 disable in test mode 1 is internal memory address 11 this pin drive the signal nack on parallel port ma12 / nseli 17 b external memory address 12 in test mode 1 is internal memory address 12 this pin connect the signal nselectin if parallel port is used ma13 / ninit 18 b ext ernal memory address 13 in test mode 1 is internal memory address 13 this pin connect the signal ninit if parallel port is used ma14 / naufd 19 b external memory address 14 this pin connect the signal nautofd if parallel port is used ma15 / nstb 20 b ext ernal memory address 15 this pin connect the signal nstrobe if parallel port is used ma16 - 23 / pd0 - 7 21,22,23,25,26,28 ,29,30 b external memory address 16 - 23 in test mode 0 is external instruction bits 16 - 23
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a in test mode 1 output internal instruction rom c ode 16 - 23 these pin is parallel port data pins 0 - 7 if register ppic_en is enable md0 - md7 31,32,33,34,35,36 ,38,39 b external memory data 0 - 7, smartmedia io0 - 7 in test mode 1 these pins output internal memories data bits 0 - 7 md8 - 15 41 - 49 b external memory data 8 - 15 in test mode 1 these pins output internal memories data bits 8 - 15 miscellaneous pin name pin number type description clk32k, xtal32 111,112 i o crystal pair for 32,768hz pwrf# 113 iu power - fail/battery - low detected pin to generate interrupt irq2_ in test mode 1 is internal instruction rom1 cs_ reset# 114 i chip reset signal, it also setting the test mode by md[2:0] and lcd mode by md[4:3] clkin, xtal 115,116 i o crystal pair for dsp operation power and ground pin name pin number type desc ription vdd 10,27,40,55, 80,90,105, 122 p power supply +3.3v + 0.3v
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a vss 7,24,37,58,77,96, 102,119 g ground 4.1 power - on reset initialization during power - on reset, state of the memory data line md[4:0] are latch into the W9980d`s internal configurat ion registers as device configuration information. for pull - up or pull - down a 4.7k ohm resistor is connect to vdd or vss. the configuration is used for lcd mode and for chip test/diagnostic. in normally function all these five pin should pull - up.
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a power - on reset configuration md bit value description md4 0 1 the lcd driver inverse the lcd segment display on/off the lcd driver display segment on/off normally md3 0 1 external serial lcd driver enable. in this mode pin56,57 are lcd function and disable ua rt function external lcd disable and pin 56,57 are uart function md2 - 0 000 001 010 011 100 111 test mode 0. all internal rom/ram are disable, dsp access instruction/data from external memory test mode 1. this mode is used to test internal memory all internal memory can be access by external pin test mode 2. internal long counter test. split these counter into several part and gpio0 - 7 show the result test mode 3. in this mode the instruction always from external test mode 4. stack test. to test the st acks on psq. these stacks can be directly access by memory pin normal mode
no.: version: page: the above informa tion is the exclusive intellectual property of winbond electronics and shall not be disclosed, distributed or reproduced without permission from winbond. 1110 - 0 001 - 08 - a 5 system diagram dsp core ad/da codec lcd driver lcd panel mic flash memory keypads control logic pc uart or ppic spk serial data optioal figure 5.1 W9980d - based digital voice recorder system diagram

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